1. Field of the Invention
This invention relates to a semiconductor memory device. More specifically, this invention relates to a nonvolatile semiconductor memory device with MOS transistors each having a floating gate and a control gate.
2. Description of the Related Art
NOR and NAND flash memories have been widely used as nonvolatile semiconductor memory devices.
In recent years, a flash memory combining the features of the NOR flash memory and the NAND flash memory has been proposed. This type of flash memory has been disclosed in, for example, Wei-Hua Liu, “A 2-Transistor Source-select (2TS) Flash EEPROM for 1.8-V-Only Application,” Non-Volatile Semiconductor Memory Workshop 4.1, 1997. A flash memory of this type (hereinafter, referred to as a 2Tr flash memory) has memory cells each of which includes two MOS transistors. In such a memory cell, one MOS transistor, which functions as a nonvolatile memory section, includes a control gate and a floating gate and is connected to a bit line. The other MOS transistor, which is connected to a source line, is used to select a memory cell.
A 2Tr flash memory operates using a positive voltage and a negative voltage. Therefore, a conventional configuration has the following problem particularly in an erase operation: a high voltage is applied to the gate insulting films of the select MOS transistors, which impairs the reliability of the memory cells.